Nonvolatile memory devices are widely incorporated in portable equipment such as cellular phones and digital cameras, and the uses thereof have rapidly expanded. In recent years, with increase of the occasion of handling audio data and video data, nonvolatile memory devices larger in capacity and operating at higher speed than conventionally attained have come to be demanded intensely. Also, because of their uses in portable equipment, demands for lower power have been further intensified.
Under the background described above, flash memory, which controls charge accumulated at a floating gate to store data, is currently the mainstream of the nonvolatile memory devices. The flash memory, structured to accumulate charge at a floating gate in a high electric field, is so complicated in cell structure that many problems arise in attainment of higher integration. Moreover, for rewrite, it is always necessary to erase a predetermined block at a time. A very long time is therefore required for rewrite and attainment of higher speed is restricted.
As next-generation nonvolatile memory devices that solve the above problems, there are ones using variable resistance elements for recording information by way of a change in electric resistance. As nonvolatile memory devices using variable resistance elements, proposed are a magnetic RAM (MRAM), an ovonic unified memory (OUM), a resistance control nonvolatile RAM (RRAM) and the like.
An example of a control method for a RRAM element, in particular, is disclosed in Japanese Laid-Open Patent Publication No. 2004-185756 (Patent Document 1), which will be described with reference to FIG. 9.
FIGS. 9(a) to 9(c) are views showing a control method for a memory cell. In either of the views, a high-level ON voltage is being applied to the word line to put a selection transistor T1 in the ON state.
FIG. 9(a) is a view showing the voltage pulse applied state at the time of write operation. The source line is set at 0 V, and a positive write pulse having a predetermined write voltage amplitude is applied to the bit line to write desired data in a variable resistance element 1. When multi-value information is to be written in the variable resistance element 1, the voltage amplitude of the write pulse is set at the level corresponding to the number of data units to be written. For example, when 4-value data is to be written in one variable resistance element 1, one among four predetermined voltage amplitudes determined according to each write data unit is selected to perform write operation. As the write pulse width, an appropriate width corresponding to the element is selected.
FIG. 9(b) is a view showing the voltage pulse applied state at the time of erase operation. During erase, 0 V is applied to the bit line, and a positive erase pulse having an erase voltage amplitude is applied to the source line. With the application of the erase pulse, the electric resistance of the variable resistance element 1 becomes the minimum value. When 0 V is applied to a plurality of bit lines and simultaneously an erase pulse is applied to source lines for corresponding memory cells, the plurality of memory cells connected with the plurality of bit lines and the source lines are erased at a time simultaneously.
FIG. 9(c) is a view showing the voltage pulse applied state at the time of read operation. During readout of data stored in the variable resistance element 1, the source line is set at 0 V, and a predetermined read voltage is applied to a selected bit line via a read circuit. The level of the bit line is then compared with a reference level for readout by a comparison determination circuit, to thereby read stored data.
In the control method described above, ON resistance actually exists in the transistor T1. The voltage applied to the element is therefore a voltage value divided according to the ON resistance and the element resistance. In other words, in the control method in FIG. 9, provided is a drive circuit that uses the drive voltage as the voltage source and has the ON resistance of the transistor as drive impedance. In general, the ON resistance is desirably sufficiently small with respect to the element resistance. During readout of stored data, in particular, the ON resistance affects the signal quality of a read signal. This problem is disclosed in Japanese Laid-Open Patent Publication No. 2004-186553 (Patent Document 2), which describes a method for reducing ON resistance to a minimum with respect to the element resistance value while minimizing increase in memory array area.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-185756
Patent Document 2: Japanese Laid-Open Patent Publication No. 2004-186553